Non-volatile memory integrated circuit chips are well known in the art. One type of a non-volatile memory cell is of a split gate type, see for example U.S. Pat. Nos. 5,029,130 and 5,572,054, whose disclosures are incorporated herein in their entirety. In these references, each memory cell is a split gate floating gate type cell. A semiconductor substrate is of a first conductivity type. A cell has a first region in the substrate of a second conductivity type. The cell further has a second region in the substrate of the second conductivity type, spaced apart from the first region, to define a channel region therebetween. A floating gate is insulated and spaced apart from a first portion of the channel region and controls the conduction of current through that portion. A control gate is spaced apart from the floating gate and is insulated and spaced apart from a second portion of the channel region and controls the conduction of the current through that portion. The cell is erased by the mechanism of Fowler Nordheim tunneling of charges from the floating gate to the control gate.
The control gates of all the cells lying in the same row are connected together to form a word line. Thus, erasure occurs by applying an erase voltage to one or more word lines erasing all the cells connected to that word line(s).
In the prior art it is also known that such split gate memory cells can be weakly erased, caused by process variation. The weakly erased cells can cause yield loss, data retention, and cycling problems.
In the prior art, one solution to fix the problem of weakly erased cells is to provide for redundant rows or sectors of cells to replace the rows or sectors containing the weakly erased cells. However, redundant rows or sectors is costly in that they occupy precious die area. In addition, they may not be enough if the failure rate of weakly erased cells is high.
In another prior art solution, the weakly erased cells are subject to further repeated erase operation interspersed with a verification (or read) operation to determine if the weakly erased cells have been fully erased. Thus, the operation of erase, verify, erase, verify is repeated. This “solution,” however, takes longer time.
Finally, the prior art teaches the mapping out of the weakly erased sectors or rows containing the weakly erased cells, and not using those sectors or rows. This has the disadvantage of reducing the size of the memory that is available for usage.
Accordingly, there is a need to solve the problem of weakly erased cells, without considerable cost, or taking a long time, or reducing the capacity of the memory array.